View HY27UK08BGFM_3227754.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.0 / feb. 2007 1 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 32gb nand flash HY27UK08BGFM
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash document title 32gbit (4gx8bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. feb. 09. 2007 initial
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : HY27UK08BGFM memory cell array = (2k+ 64) bytes x 64 pages x 16,384 blocks page size - x8 device : (2k + 64 spare) bytes : HY27UK08BGFM block size - x8 device: (128k + 4k spare) bytes page read / program - random access: 25us (max.) - sequential access: 30ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - 1st cycle: manufacturer code - 2nd cycle: device code. chip enable don't care - simple interface with microcontroller serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles (with 1bit/512byte ecc) - 10 years data retention package - HY27UK08BGFM-tp : 48-pin tsop dsp (12 x 20 x 2.3 mm) - hHY27UK08BGFM-tp (lead free)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 1. summary description the hynix HY27UK08BGFM series is a 4gx8bit capacity . the device is offered in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 16,384 blocks, composed by 64 pages co nsisting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128k-byte block. data in the page mode can be read out at 30ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce , we , ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp input pin. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multi- ple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of the HY27UK08BGFM extended reliability of 100k program/ erase cycles by providing ecc (error correcting code) with real time mapping-out algorithm. the chip could be offered with the ce don?t care function. this function allows the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not st op the read operation. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features li ke otp/unique id area, read id2 extension. the HY27UK08BGFM is available in 48 - tsop1 - dsp 12 x 20 mm package. 1.1 product list part number orization vcc range package HY27UK08BGFM x8 2.7v - 3.6 volt 48tsop1
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure1: logic diagram 9&& 966 :3 &/( $/( 5( :( &( ,2a,2 5% io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection table 1: signal names
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 1& 1& 1& 5% 5% 5% 5% 5( &( &( 1& 9ff 9vv &( &( &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk '63 [ figure 2. 48tsop1 - dsp contactions, x8 device (4ce)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 1.2 pin description pin name description io0-io7 data inputs/outputs the io pins allow to input comma nd, address and data and to outp ut data during read / program operations. the inputs are latched on th e rising edge of write enable (we ). the i/o buffer float to high-z when the device is desele cted or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the addres s register on the rising edge of write enable (we ). ce 1, ce 2 chip enable this input controls the selection of th e device. when the device is busy ce 1, ce 2 low does not deselect the memory. ce 3, ce 4 chip enable the input enable the second hy27uw08ag5m we write enable this input acts as clock to latch command, addres s and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out control, and when active drives the data on to the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protec tion against undesired modify (program / erase) operations. r/b 1 / r/b 2 r/b 3 / r/b 4 ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection table 2: pin description note: 1. a 0.1uf capacitor should be connected between the v cc supply voltage pin and the vs s ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash function 1st cycle 2nd cycle 3rd cycle acceptable command during busy read 1 00h 30h - read for copy-back 00h 35h - read id 90h - - reset ffh - - yes page program (start) 80h 10h - copy back pgm (start) 85h 10h - cache program 80h 15h - block erase 60h d0h - read status register 70h - - yes random data input 85h - - random data output 05h e0h - cache read start 00h 31h - cache read exit 34h - - table 4: command set table 3: addre ss cycle map(4ce) 1. l must be set to low. io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 5th cycle a28 a29 a30 l (1) l (1) l (1) l (1) l (1)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash cle ale ce we re wp mode h l l rising h x read mode command input l h l rising h x address input(5 cycles) h l l rising h h write mode command input l h l rising h h address input(5 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 5: mode selection note: 1. with the ce high during latency time does not stop the read operation
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 4 and table 12 for details of the timings requirements. command codes are always applied on io7:0, disregarding th e bus configuration. 2.2 address input. address input bus operation allows the insertion of the memo ry address. to insert the 30 addresses needed to access the 16gbit 5 clock cycles are needed. addresses are accepted with chip enable low, address latch enable high, com- mand latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protec t pin must be high. see figure 5 and table 12 for details of the timings requirements. addresses are always appl ied on io7:0, disregarding the bus configuration. 2.3 data input. data input bus operation allows to feed to the device the data to be programm ed. the data insertion is serially and timed by the write enable cycles. data are accepted only wi th chip enable low, addre ss latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 6 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the memory array and to chec k the status register content, the id data. data can be serially shifted out toggling the read enab le pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figures 7,9,10 and table 12 for details of the timings require- ments. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 3. device operation 3.1 page read. page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. in two consecutive read operations, the second one doesn?t? ne ed 00h command, which five address cycles and 30h com- mand initiates that operation. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 21 12 bytes of data within the selected page are transferred to the data registers in less than 25us(tr ). the system controller ma y detect the completion of this data transfer (tr) by analyzing the output of r/b pin. once the data in a page is load ed into the data registers, they may be read out in 30ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device out- put the data starting from the selected colu mn address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out- put command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. 3.2 page program. the device is programmed basically by page, but it does allo w multiple partial page programming of a word or consec- utive bytes up to 2112 , in a single page program cycle. the number of consecutive partial page programming operat ion within the same page without an intervening erase operation must not exceed 8; for example, 4 times for main array and 4 times for spare array. the addressing should be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 2112bytes of data may be load ed into the data register, followed by a non-volatile pro- gramming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input comma nd (80h), followed by the five cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input co mmand (85h). random data input may be operated multi- ple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the prog ramming process. writing 10h alone without previously entering the serial data will not initia te the programming process. the internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status regi ster command may be entered to read the status register. the system controller can detect the completi on of a program cycle by monitoring the r/b output, or the status bit (i/ o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully prog rammed to "0"s. the command register remains in read sta- tus command mode until another valid co mmand is written to the command register. figure 13 details the sequence.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 3.3 block erase. the erase operation is done on a block basis. block address loading is accompli shed in three cycles initiated by an erase setup command (60h). only address a18 to a30 is va lid while a12 to a17 is ignored. the erase confirm com- mand (d0h) following the block address loading initiates the in ternal erasing process. this two-step sequence of setup followed by execution command ensures th at memory contents are not accidental ly erased due to external noise con- ditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. once the erase process starts, the read status register command may be entered to read the status reg- ister. the system controller can detect the co mpletion of an erase by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid wh ile erasing is in progress. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 18 details the sequence. 3.4 copy-back program. the copy-back program is configured to quickly and efficien tly rewrite data stored in on e page without utilizing an external memory. since the time -consuming cycles of serial access and re-l oading cycles are removed, the system per- formance is improved. the benefit is espe cially obvious when a portion of a bloc k is updated and the rest of the block also need to be copied to the newl y assigned free block. the operation for performing a copy-back program is a sequential execution of page-read with out serial access and copying-program wi th the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte data into the inter- nal data buffer. as soon as the device returns to ready st ate, copy back command (85h) with the address cycles of destination page may be written. the program confirm comm and (10h) is required to actually begin the programming operation. data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in figure 15. "when there is a program-failure at copy-back operatio n, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit e rror due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 15 shows the command sequ ence for the copy-back operation. the copy back program operation requires three steps: 1. the source page must be read using the read a co mmand (one bus write cycle to setup the command and then 5 bus write cycles to input the source page address). th is operation copies all 2kbytes from the page into the page buffer. 2. when the device returns to the re ady state (ready/busy high), the seco nd bus write cycle of the command is given with the 5bus cycles to input the target page a ddress. a30 must be the same for the source and target pages. 3. then the confirm command is issu ed to start the p/e/r controller. note: 1. copy-back program operation is allowe d only within the same memory plane. 2. on the same plane, it?s prohibited to operate copy-b ack program from an odd address page (source page) to an even address page (target page) or from an even addre ss page (source page) to an odd address page (target page). therefore, the copy-back program is permitted just between odd address pages or even address pages.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or eras e operation is completed successfully. after writing 70h command to the com- mand register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. see figure 9 for details of the read status operation. 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially output the manufacturer co de (adh), and the device code and 3rd cycle id, 4th cycle id, respectively. the command register re mains in read id mode until further commands are issued to it. figure 19 shows the operation sequen ce, while tables 15 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the st atus register is cleared to value e0h when wp is high. refer to table 13 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst afte r the reset command is written. refer to figure 24.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 3.8 cache program. cache program is an extension of page program, which is ex ecuted with 2112byte data regi sters, and is available only within a block. since the device has 1 pa ge of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. after writin g the first set of data up to 2112byte into the selected cache registers, cache program command (15h) instead of actu al page program (10h) is input to make cache registers free and to start internal program operation. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time (tcbsy) an d has its cache registers ready for the next data-input while the internal programming gets started wi th the data loaded into data register s. read status command (70h) may be issued to find out when cache registers become ready by polling the cache-bu sy status bit (i/o 6). pass/fail status of only the previous page is available upon the return to ready state. when the ne xt set of data is input with the cache program command, tcbsy is affected by the progress of pending internal programming . the programming of the cache registers is initiated only when th e pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to identify the com- pletion of internal programming. if the system monitors the progre ss of programming only with r/b , the last page of the target programming sequence must be programmed with actual page program command (10h). if the cache program command (15h) is used instead, status bit (i/o5) must be polled to find out when the last programming is actually finished before starting other operations such as read. pass/fail status is available in two steps. i/o 1 returns with the status of the previous page upon ready or i/o6 status bit chan ging to "1", and later i/o 0 with the st atus of current page upon true ready (returning from internal programming) or i/o 5 status bit ch anging to "1". i/o 1 may be read together when i/o 0 is checked. see figure 16 for more details. note : since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completi on of the previous cycle, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) the value for a30 from second to the last page address mu st be same as the value gi ven to a30 in first address.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 3.9 cache read cache read operation allows automatic download of consecut ive pages, up to the whole device. immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. start address of 1st page is at page start (a<10:0>=00h), af ter 1st latency time (tr) , automatic data download will be uninterrupted. in fact latency time is 25us, while download of a page require at least 100us for x8 device. cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - r/b ( ?0? means latency ongoing, download not possible, ?1? means download of n page possible, even if device internally is active on n+1 page - status register (sr<6> behave like r/b , sr<5> is ?0? when device is internally reading and ?1? when device is idle) to exit cache read operation a cache read exit command ( 34h) must be issued. this command can be given any time (both device idle and reading). if device is active (sr<5>=0) it will go idle within 5us, whil e if it is not active, device itself will go busy for a time shorter then trbsy before becoming again idle and ready to accept any further commands. if user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. random data output is not available in cache read. cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 4. other features 4.1 data protection & power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all function s whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at vil during power-up and power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 25. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back, cache program and ra ndom read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it re turns to high when the internal controller has finished the operation. the pin is an open-drain dr iver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig 26). its valu e can be determined by the following guidance.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash parameter symbol min typ max unit valid block number n vb 32128 32768 blocks table 6: valid blocks number note: 1. the 1st block is guaranteed to be a valid bl ock up to 1k cycles with ecc. (1bit/512bytes) symbol parameter value unit t a ambient operating temperature (commercial temperature range) 0 to 70 ambient operating temperature (extended temperature range) -25 to 85 ambient operating temperature (industry temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v io (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 7: absolute maximum ratings note: 1. except for the rating ?operating temperature rang e?, stresses above those listed in the table ?absolute maximum ratings? may cause perm anent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sectio ns of this specification is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tran sition and for less than 20ns during transitions.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 *elw*elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( $a$ figure 3: block diagram
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash parameter symbol test conditions min typ max unit operating current sequential read i cc1 t rc =30ns ce =v il , i out =0ma -2535ma program i cc2 - - 25 35 ma erase i cc3 - - 25 35 ma stand-by current (ttl) i cc4 ce =v ih , wp =0v/vcc -3ma stand-by current (cmos) i cc5 ce =vcc-0.2, wp =0v/vcc - 80 400 ua input leakage current i li v in= 0 to vcc (max) - - 80 ua output leakage current i lo v out =0 to vcc (max) - - 80 ua input high voltage v ih - vccx0.8 - vcc+0.3 v input low voltage v il - -0.3 - vccx0.2 v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current (r/b ) i ol (r/b ) v ol =0.4v 8 10 - ma table 8: dc and operating characteristics parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load (2.7v - 3.6v) 1 ttl gate and cl=30pf table 9: ac conditions
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash parameter symbol min typ max unit program time t prog - 200 700 us dummy busy time for cache program t cbsy - 3 700 us dummy busy time for cache read t rbsy -5-us number of partial program cycles in the same page main array nop - - 4 cycles spare array nop - - 4 cycles block erase time t bers -23ms table 11: program / erase characteristics item symbol test condition min max unit HY27UK08BGFM-t(p) input / output capacitance c i/o v il =0v - 80 pf input capacitance c in v in =0v - 80 pf table 10: pin capacitance (ta=25c, f=1.0mhz)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash parameter symbol min max unit cle setup time tcls 15 ns cle hold time tclh 5 ns ce setup time tcs 25 ns ce hold time tch 5 ns we pulse width twp 15 ns ale setup time tals 15 ns ale hold time talh 5 ns data setup time tds 15 ns data hold time tdh 5 ns write cycle time twc 30 ns we high hold time twh 10 ns address to data loading time tadl (2) 100 ns data transfer from cell to register tr 25 us ale to re delay tar 15 ns cle to re delay tclr 15 ns ready to re low trr 20 ns re pulse width trp 15 ns we high to busy twb 100 ns read cycle time trc 30 ns re access time trea 25 ns re high to output high z trhz 50 ns ce high to output high z tchz 50 ns cache read re high tcrrh 100 ns re high to output hold trhoh 15 ns re low to output hold trloh 5 ns ce high to output hold tcoh 15 ns re high hold time treh 10 ns output high z to re low tir 0 ns ce access time tcea 30 ns we high to re low twhr 60 ns device resetting time (read / program / copy-back program / erase) trst 5/10/40/500 (1) us write protection time tww (3) 100 ns table 12: ac timing characteristics note: 1. if reset command (ffh) is written at ready st ate, the device goes in to busy for maximum 5us 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 3. program / erase enable operation : wp high to we high. program / erase disable operation : wp low to we high.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash io page program block erase cache program read cache read coding 0 pass / fail pass / fail pass / fail (n) na pass: ?0? fail: ?1? 1 na na pass / fail (n-1) na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy p/e/r controller bit ready/busy p/e/r controller bit active: ?0? idle: ?1? 6 ready/busy ready/busy cache register free ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect write protect protected: ?0? not protected: ?1? table 13: status register coding device identifier cycle description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, numb er of simultaneously programmed pages. 4th page size, block size, spare size, organization table 14: device identifier coding part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) 3rd cycle 4th cycle HY27UK08BGFM 3.3v x8 adh d3h c1h 95h table 15: read id data table
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash description io7 io6 io5 io4 io3 io2 io1 io0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program belween multiple chips not support support 0 1 cache program not support support 0 1 table 16. 3rd byte of devi ce identifier description description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1k 2k reserved reserved 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 block size (without spare area) 64k 128k 256k reserved 0 0 0 1 1 0 1 1 organization x8 x16 0 1 table 17: 4th byte of devi ce identifier description
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 4: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 1& 1& 1& 1& 1& 5% 5% 5( &( &( 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ w&/6 w&6 w:3 w:& w:& w:& w:3 w:3 w:3 w$/6 w:+ w:+ w:+ w:+ w$/+ w$/6 w$/6 w$/6 w$/6 &ro$gg w$/+ w$/+ w$/+ w$/+ w'+ &ro$gg 5rz$gg 5rz$gg 5rz$gg w:& w'+ w'+ w'+ w'+ w'6 w'6 w'6 w'6 w'6 &/( &( :( $/( ,2[ figure 5: address latch cycle figure 6: input data latch cycle w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( 1rwhv ',1ilqdophdqv
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 7: sequential out cycle after read (cle=l, we =h, ale=l) w5& &( 5( ,2[ 5% w5($ w55 'rxw 'rxw 'rxw 1rwhv7udqvlwlrqlvphdvxuhgp9iurpvwhdg\vwdwhyrowdj hzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] w5($ w5+= w5+= w5($ w&+= w&2+ w5+2+ w5(+ w5& w53 w5(+ w5($ w&($ w5/2+ w55 w5($ w&+= w&2+ w5+= w5+2+ 'rxw 'rxw &( 5( ,2[ 5% 1rwhv7udqvlwlrqlvphdvxuhgp9iurpvwhdg\vwdwhyrowdj hzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] figure 8: sequential out cycle after read (edo type cle=l, we =h, ale=l)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 9: status read cycle w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &($ w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ kru%k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( $/( &( ,2[ :( 5( 5% w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= 5rz$gg figure 10: read1 operation (read one page)
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash w:% w$5 w&+= w&2+ w5& w5 w55 %xv\ k k 'rxw 1 'rxw 1 'rxw 1 &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &roxpq$gguhvv 5rz$gguhvv &/( &( :( $/( 5( ,2[ 5% figure 11: read1 operation intercepted by ce
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ w5+: figure 12 : random data output
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 13: page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro $gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp xswrp%\wh 6huldo,qsxw &ro $gg 5rz $gg 5rz $gg 5rz $gg 'lq 1 'lq 0 k k ,2r w:& w:% w352* w:& w$'/
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5zr$gg 5zr$gg 5zr$gg w:& w:% w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg w:& w$'/ w$'/ figure 14: random data in
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash %xv\ w:% w:% w$'/ w352* w:& &/( &( :( 5( ,2[ 5% $/( &roxpq$gguhvv k k k 'dwd 'dwd1 k ,2[ %kk &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg 5rz$gguhvv &roxpq$gguhvv 5rz$gguhvv w5 %xv\ &rs\%dfn'dwd ,qsxw&rppdqg figure 15: copy back program
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( 5% ,2[ ([&dfkh3urjudp w:& k k ,2 3urjudp&rqilup &rppdqg7uxh /dvw3djh,qsxw 3urjudp 0d[wlphvuhshdwdeoh w&%6<pd[xv w&%6< &ro$gg 5rz$gg'dwd w&%6< w&%6< w352* 6huldo'dwd &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 3urjudp &rppdqg 'xpp\ k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw k k k k k k k k k 'lq 1 'lq 0 'lq 1 'lq 0 &ro$gg &ro$gg 5rz$gg 5rz$gg &ro$gg &ro$gg 5rz$gg 5rz$gg w:% w352* w:% w&%6< figure 16: cache program
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash k $gg $gg $gg $gg $gg k ' ' ' ' ' ' ' ' w&55+ 5hdgvwsdjh 5hdgqgsdjh ' ' &/( $/( ,2; 5% 5( :( figure 17 : cache read re high
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 'k 5rz $gg 5rz $gg 5rz $gg k $xwr%orfn(udvh 6hwxs&rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 5rz$gguhvv figure 18: block erase op eration (erase one block) k &/( &( :( $/( 5( ,2[ k w5($ 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k wk&\foh ug&\foh 'k &k k w$5 figure 19: read id operation
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 'k ' 5hdgvwsdjh 5hdgqgsdjh 5hdgugsdjh 5hdgwksdjh ,goh ,goh ' ' ' ' ' ' ' ' ' ' ' ' $gg $gg $gg $gg $gg k ?v ?v ?v ?v ?v ?v ?v &/( $/( :( 5( ,qwhuqdorshudwlrq 6wdwxv5hjlvwhu 65! figure 20: start address at page start :a fter 1st latency uninterrupted data flow ' ,goh ,goh ?vw 5%6< qsdjh qsdjh 5hdgqsdjh ' ' k ' ' ' ' &/( $/( :( 5( 5% ,qwhuqdo rshudwlrq 6wdwxv5hjlvwhu 65! 8vhufdq khuhilqlvk uhdglqj1 sdjh 1sdjh fdqqrweh uhdg ?v ?v ,qwhuuxswhg 5hdg qsdjh figure 21: exit from cache read in 5u s when device internally is reading
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash system interface using ce don?t care to simplify system interface, ce may be deasserted during data loading or sequential data-reading as shown below. so, it is possible to connect nand flash to a microporcess or. the only function that wa s removed from standard nand flash to make ce don?t care read operation was disabling of the automatic sequential read function. &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ figure 22: program operation with ce don?t-care. ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 figure 23: read operation with ce don?t-care.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 24: reset operation ))k w 567 :( $/( &/( 5( ,2[ 5% :3 :( 9ff xv w 9 7+ figure 25: power on and data protection timing vth = 2.5 volt for 3.3 volt supply devices
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 5sydoxhjxlghqfh 5splq9sduw zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ & / 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 2+ wu wi 9 2/ 9 2/ 99 2+ 9 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 26: ready/busy pin electrical specifications
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 27: page programming within a block m???g???gszig????g??gtzig???? kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a ozyp a ozp oyp oxp l?upgy?????g????g???????gow??????????p kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a oxp a ozp ozyp oxp
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affe ct the performance of valid blocks becaus e it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the lo cations inside valid blocks erased(ffh). the bad block information is wr itten prior to shipping. any block where the 1st byte in the spare area of the 1st or 2nd page(if the 1st page is bad) does not cont ain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block inform ation may be erased. for the sy stem to be able to recog- nize the bad blocks based on the original information it is recommended to create a bad block table following the flow- chart shown in figure 28. the 1st block, which is placed on 00h block address is guaranteed to be a valid block. bad replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. the copy back program command can be us ed to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 18 for the recommended procedure to follow if an error occurs during an operation. operation recommended procedure erase block replacement program block replacement or ecc (with 1bit/512byte) read ecc (with 1bit/512byte) table 18: block failure <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh figure 28: bad block management flowchart
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 29~32) :: w k k :( ,2[ :3 5% k k w :: :( ,2[ :3 5% figure 29: enable programming figure 30: disable programming
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 31: enable erasing figure 32: disable erasing
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash 5. appendix : extra features 5.1 addressing for program operation within a block, the pages must be prog rammed consecutively from lsb (least sign ificant bit) page of the block to msb (most significant bit) page of the block. random address programming is prohibited. 5.2 stacked devices access a small logic inside the devices allows th e possibility to stack up to 4 devices in a single package without changing the pinout of the memory. to do this the in ternal address register can store up to 30 addresses(512mbyte addressing field) and basing on the 2 msb pattern each devi ce inside the package can decide if re main active (1 over 4 ) or ?hang up? the connection entering the stand-by.
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash figure 33. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline ' h % $ $ ( & ( / &3 . table 19: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters min typ max a 2.300 a1 0.050 0.150 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5
rev. 0.0 / feb. 2007 preliminary HY27UK08BGFM series 32gbit (4gx8bit) nand flash marking information - tsop1 packag marking example tsop1 k o r h y 2 7 u k 0 8 b g f m x x x x y w w x x - hynix - kor - HY27UK08BGFM xxxx hy: hynix 27: nand flash u: power supply k: classification 08: bit organization bg: density f: mode m : version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix sym bol : origin country : u(2.7v~3.6v) : single level cell+ dsp+ large block : 08(x8) : 32gbit : f (4nce & 4r/nb; sequential row read disable) : 1st generation : t(48-tsop1) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) m(-30 ~85 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part num ber

▲Up To Search▲

Price & Availability of HY27UK08BGFM

	To Download HY27UK08BGFM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .